1. Field of Use
This invention relates generally to data processing systems and more particularly to error detection and correction apparatus included within the memory of a data processing system.
2. Prior Art
It is well known to utilize metal oxide semiconductor field effect transistor (MOSFET) memory elements in main memory systems. Since such memories are volatile in nature and require continual restoration of the stored information, error detection and correction apparatus are normally included within such memory systems for ensuring the integrity of the stored information. Generally, main storage systems utilize a modified Hamming code for single error detection/double error detection. Normally, such codes increase significantly the number of memory circuits.
In order to increase memory reliability notwithstanding attendant increases in error detection and correction circuits, at least one system utilizes codes which improve upon the modified Hamming SEC/DED codes and simplify the memory circuit implementation as well as provide faster and better error detection capability. This arrangement is described in a paper "A Class of Optimal Minimum Odd-Weight-Column SEC/DED Codes" by M. Y. Hsiao which appears in the publication "IBM Journal of Research and Development", July, 1970. The construction of such codes is described in terms of a parity check matrix H. The selection of the columns of the H matrix for a given (n, k) code is based upon the following constraints:
1. Every column should have an odd number one's; PA1 2. The total number of one's in the H matrix should be a minimum; and, PA1 3. The number of one's in each row of the H matrix should be made equal or as close as possible to the average number.
Errors are indicated by analyzing the syndromes formed from the data amd check code bits. An odd number of syndrome bits indicates a single error while an even number of syndrome bits indicate a double or uncorrectable error.
In general, operations for decoding or encoding data and check bits in prior art memory systems proceed as follows. Normally, during a read operation, a word is read from a main memory location and the data bits together with check code bits are stored in a data storage register. Byte parity bits are generated from the data bits. The syndromes formed from the data and code check bits are analyzed. If no error is indicated, the byte parity encoded data is transmitted onto the data bus. If a double code error is indicated, a program interrupt signal is generated and the error data are made available for program analysis. In the case where a single error is signalled, the correction circuits correct the data.
In the case of a write operation, the byte encoded parity word is received from the data bus and the check code bits are generated for the SEC/DED code. The received byte parity bits are examined for validity. When no error is detected, the coded word is stored into a memory location. In the event of a double error, the write operation is aborted and the data processing system is notified of the error.
Additionally, such prior art memory systems are required to perform "partial write" operations. The partial write operation occurs when a portion of data word (i.e., a byte) stored in memory is read out and altered by new data and thereafter written into memory. Prior art memory systems handle partial write operations similar to that described above. That is, the data to be written into memory is checked. When a double error is indicated, the operation is aborted and the data processing system is notified.
The above arrangements have been found to be unsuitable for use in systems where data is transferred along a common data bus at a rapid rate. In such instances, by the time the parity encoded data word can be checked, the data source applying the data will have relinquished its control of the bus. Accordingly, the arrangement requires that the sending source be connected to the bus until the parity encoded data can be checked. This results in reducing the overall throughput of the data processing system.
Also, at least one of the above mentioned prior art systems has employed an arrangement which utilizes address parity bits as data bits and includes such bits in the generation of check code bits. While the arrangement is able to signal when an incorrect location is being accessed, the address parity bits provide no indication regarding the integrity of the data being written into memory.
Accordingly, it is a primary object of the present invention to provide an improved method and apparatus for detecting and correcting parity encoded data applied from any one of a plurality of input/output sources for storage in a memory system.
It is another object of the present invention to provide an improved method and apparatus for use in a memory system connected to operate with a high speed common bus system.
It is still a further object of the present invention to provide an arrangement for detecting and correcting errors in a manner which requires a minimum of additional circuits.